
MAX5101
+2.7V to +5.5V, Low-Power, Triple, Parallel
8-Bit DAC with Rail-to-Rail Voltage Outputs
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5
POSITIVE SETTLING TIME
MAX5101-08
1
s/div
CH1
CH2
CH1 = WR, 2V/div
CH2 = VOUTA, 2V/div
DAC CODE FROM 10 TO F0 HEX
NEGATIVE SETTLING TIME
MAX5101-09
1
s/div
CH2
CH1
CH1 = WR, 2V/div
CH2 = VOUTA, 2V/div
DAC CODE FROM F0 TO 10 HEX
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
032
6496
128
160 192
224 256
INTEGRAL AND DIFFERENTIAL NONLINEARITY
vs. DIGITAL CODE
MAX5101-10
DIGITAL CODE
INL/DNL
(LSB)
RL =
∞
DNL
INL
Typical Operating Characteristics (continued)
(VDD = +3V, RL = 10k
, CL = 100pF, code = FF hex, TA = +25°C, unless otherwise noted.)
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(0 TO 1 DIGITAL TRANSMISSION)
MAX5101-06
200ns/div
CH2
CH1
CH1 = D7, 2V/div
CH2 = VOUTA, 1mV/div, AC-COUPLED
0 TO 1 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH)
DIGITAL FEEDTHROUGH GLITCH IMPULSE
(1 TO 0 DIGITAL TRANSMISSION)
MAX5101-07
200ns/div
CH2
CH1
CH1 = D7, 2V/div
CH2 = VOUTB, 1mV/div, AC-COUPLED
1 TO 0 DIGITAL TRANSITION ON
ALL DATA BITS (WITH WR HIGH)